FIGS. 1 and 2 show cross sectional portions of a prior art trench n-type MOSFET device (FIG. 1) and a prior art surface gate MOSFET device (FIG. 2). In FIG. 1 the MOSFET includes a gate region constructed inside a trench with gate dielectric located on all its sides. The trench is filled with polysilicon that is used as a gate electrode. Source connection is achieved using thick top metal, through the gate-source dielectric opening, by direct silicon source and body regions contact. The backside of the N+ substrate is used as a drain contact. Current travel in a vertical direction from the source regions, along a channel parallel to the sidewalls of the gate trench and to the backside drain. FIG. 2 shows a similar prior art N-channel MOSFET in planar form. The gate region now is formed on top of the silicon surface instead of being recessed in the trench. Current also flows vertically from the source regions, beneath the gate and to the backside drain. While the drawings show construction of only one MOSFET, those skilled in the art understand it is conventional to repeat the structure of a typical device many times to form an array of devices. The array may be configured in various cellular or stripe layouts currently used by the industry. These types of devices have been long known. Recent manufacturing improvements have increased the densities of the trench gated devices. Higher density is desired because it allows manufacturers to make devices that are smaller but handle high currents. However, the increased density does not significantly improve power loss in mid to high ranged devices of 60 volts to 2000 volts. Since most of the loss is due to epi resistivity, which is set by desired breakdown voltage, the power losses are caused by the high resistivity of the drain regions. The resistivity of the drain must be kept high in order to block the device from conducting when the gate is turned off. However, a high resistivity for blocking voltage has the unwanted effect of increasing the on-resistance of the device. As a result, the denser devices have significant power loss. Since a high blocking voltage is a critical feature of power MOSFETs, increasing drain doping is not an option. Others have attempted to solve this problem by providing layers of alternate conductivity between the source regions and the drain. For examples of conventional solutions see U.S. Pat. Nos. 5,216,275 and 5,438,215. The layers of alternating conductivity increase the breakdown voltage of the device and thus allow for higher doping of the drain zone to reduce the on-resistance. However, the prior art solutions have drawbacks. In both patents the alternating layers are inserted before all diffused regions are formed. As these regions are activated with a thermal diffusion step, the alternating layers also diffuse. Some of the alternating layers are made by trenching and epitaxial deposition of doped silicon. Those structures are unreliable and often crack or separate during subsequent processing. This reduces their effectiveness.
In order to reduce drain resistance without affecting the device blocking capability, an additional opposite polarity doping zone is added and spaced next to the drain zone. This zone extends from the top surface and it is shorted to the upper source metal. The zone is added after all of the thermal diffusions steps are completed and activated. In order to create this zone and minimize the lateral diffusion of dopants into the upper drain region spaced next to it, a new method is proposed which includes trench silicon etching, doping and dielectric trench fill. The zone is constructed using conventional trench techniques. The exposed trench sidewalls are doped from a solid, liquid or gaseous source and the trench is filled with an insulator that is deposited at low temperature. When the device is in the blocking state both zones will contribute charges with opposite signs, but the induced fields in both zones will cancel out. This allows for use of a much higher doping for both zones and specifically in the drain zone. Current flowing through drain zone now sees a much lower resistance drop which in turn will reduce the device overall on-resistance and improve its efficiency.
The invention provides a unique structure for a MOS-gated semiconductor device. The structure includes a substrate of semiconductor material having opposite top and bottom surfaces. The top surface has a pair of well regions of a first conductivity and a pair of source regions of a second conductivity. A gate and channel region are located between the respective pairs of well and source regions. Beneath the wells and sources is a drift region of a second conductivity. The drift region is adjacent a highly doped drain a second conductivity that extends from the drift region to the opposite surface of the substrate. A pair of extended well regions extend from distal ends of the wells through a substantial portion of the drift region in a direction toward the drain region. The extended well regions are formed adjacent the sidewalls of trenches. The sidewalls are doped with dopants of a first conductivity that generate opposing induced electrical fields at their respective junctions with the drain zone. The trenches are filled with insulating material, such as silicon dioxide.
The method of trench construction is conventional. However, the timing of the trench construction is optimized by constructing the trenches after the body, well and source are in place and all other major diffusions steps are completed. Then the diffusion of the dopants from the sidewalls can be tightly controlled to generate the proper doping profile and keep the lateral diffusion close to the sidewall. The insulator that fills the trench is formed at low temperatures using, for example, conventional low temperature oxide deposition. Such a step does not adversely affect the doping profile of the extended well regions that are adjacent the sidewalls of the trenches.